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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16650
120-/128-OUTPUT TFT-LCD GATE DRIVER
The PD16650 is a TFT-LCD gate driver. Provided with a level shift circuit at the logic input, this chip can output a high gate scan voltage for a CMOS-level input. The PD16650 has an output change-over function for switching from the 120-output mode to the 128-output mode, and vice versa, thereby supporting the VGA, SVGA, and XGA panels. Its output enable function (OE) enables installing the driver on either side.
FEATURES
* Output with high dielectric strength (on/off range: VDD - VEE1 = 40 VMAX.) * Built-in shift direction change-over function * Shiftable negative supply voltage (VEE1) level (shift range: |VEE1 - VEE2| = 10 V) * Two acceptable CMOS input levels (3.3 and 5 V) * Output enable function * MC-selectable output count (MC = high: 120-output mode) (MC = low : 128-output mode) * Slim TCP
ORDERING INFORMATION
Part number Package TCP (TAB package) Standard TCP (OL pitch = 220 m)
PD16650N-xxx PD16650N-xxx
Remark When ordering, the customer can specify the external form of the TCP. Call one of our sales representatives for more information.
Document No. S11041EJ1V0DS00 (1st edition) (Previous No. IP-3677) Date Published December 1995 P Printed in Japan
(c)
1995
PD16650
BLOCK DIAGRAM
VCHA
R/L
LS
X
LS
STVR
LS
128-bit shift register
LS
STVL
MC
LS
OE
LS
VEE1
X1
X2
X127
X128
Remark LS (level shifter): Interfaces the 5 V CMOS level with the VDD-VEE2 level.
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PD16650
PIN CONNECTION DIAGRAM (PD16650N-xxx)
X128 X127 X126
VDD VCHA VEE2 STVL OE
X70 X69 X68 X67 X66 X65 (Copper foil side) X64 X63 X62 X61 X60 X59 These pins are ineffective in the 120-output mode.
X
R/L VCC MC VSS STVR VEE2 VEE1
X3 X2 X1
Caution
The VCHA pin should be connected to the VDD or VEE2 pin on the TCP. (This method eliminates the necessity to provide the VCHA input pin on the TCP, resulting in a reduction in the number of required input pins.)
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PD16650
PIN DESCRIPTION
Pin symbol X1 to X128 Pin name Driver output Description of function Output scan signals to drive the TFT-LCD gate electrodes. The output changes when the shift clock X rises. The amplitude of the driver output is VDD - VEE1. See the timing charts shown later for details of how to switch between the 120output mode and 128-output mode. MC Output count change-over input Receives a signal that changes the number of outputs. For the 120-output mode, this pin must be supplied with a high level (VCC). For the 128-output mode, it must be supplied with a low level (VSS or VEE2). VCHA Logic voltage change-over input STVR STVL Start pulse input/output Must be supplied with the VEE2 level when the logic supply voltage is 3.3 V, and with the VDD level when the logic supply voltage is 5.0 V. Receives an input to the internal shift register. The input data is loaded on the shift register at the positive-going edge of the shift clock X. The scan signals are output from X1 to X128. The input/output level is the CMOS level. Outputs a start pulse to the next stage if a cascade connection is used. In the 120-output mode, the start pulse is output at the negative-going edge of the 120th shift clock X pulse, and cleared at the negative-going edge of the 121st pulse. In the 128-output mode, the start pulse is output at the negative-going edge of the 128th shift clock X pulse, and cleared at the negative-going edge of the 129th pulse. R/L Shift direction change-over input R/L = high (for shift right): STVR X1 X128 STVL R/L = low (for shift left) : STVL X128 X1 STVR
X
Shift clock input
Receives a shift clock pulse for the internal shift register. A shift occurs at the positive-going edge of the shift clock pulse.
OE
Output enable input
When this pin is at a high level, the driver output is fixed at a low level. The shift register is not cleared, however. The internal logic circuit operates even when the pin is at a high level. synchronized with the clock. The signal supplied to this pin is not
VDD
Driver positive supply voltage
Receives the supply voltage for both the logic circuit and driver.
VCC
Reference voltage
5 0.5 V/3.3 0.3 V Reference voltage for the LS1 and LS2 level shifters.
VSS VEE1
Ground Driver negative supply voltage
Must be connected to the system ground. VEE1 (for the driver)
VEE2
Driver negative supply voltage
VEE2 (for the logic circuit)
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PD16650
CAUTIONS FOR USE
1) Power-on sequence To prevent latch-up disruption, the power must be switched on in the order: VCC VEE1 VEE2 VDD Logic input When witching off, reverse the order. This order must be observed also during transition. 2) Insertion of bypass capacitors The internal logic circuit operates at a high voltage. To make VIH and VIL immune to noise, use capacitors of 0.1 F or so between supply voltages as shown below.
VDD VCC 0.1 F VSS 0.1 F VEE2 0.1 F
3)
Negative voltage level shift If it is necessary to shift the level of a negative supply voltage, shift the VEE1 (driver supply voltage) level. The shift should be limited to within: VEE2 VEE1 VEE2 + 10 V Note that shifting the VEE1 level results in the ON-state output resistance and output fall time ratings being changed.
4)
Handling the VEE1 and VEE2 driver negative supply voltage pins For applications in which a negative supply voltage level is not shifted, connect the VEE1 pin (driver supply voltage) to the VEE2 pin (logic supply voltage) outside the TCP. Fix all unused input pins to the VEE2 level.
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PD16650
TIMING CHART (MC = VSS, 128-OUTPUT MODE, AND R/L = VCC)
X
1
2
3
127
128
129
130
STVR (STVL)
X1
X2
X3
X127
X128
STVL (STVR)
X1 at the next stage
X2 at the next stage
Caution
Do not change all outputs simultaneously, because such a sequence may result in malfunction.
6
PD16650
TIMING CHART (MC = VCC, 120-OUTPUT MODE, AND R/L = VCC)
X
1
2
3
119
120
121
122
STVR (STVL)
X1
X2
X3
X127
X128
STVL (STVR)
X1 at the next stage
X2 at the next stage
Cautions 1. Do not change all outputs simultaneously, because such a sequence may result in malfunction. 2. The output sequence in the 120-output mode is as follows: STVR (STVL) X1 X2 ... X60 X69 ... X127 X128 STVL (STVR)
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PD16650
ABSOLUTE MAXIMUM RATINGS (TA = 25 C, VSS = 0 V)
Parameter Supply voltage Supply voltage Supply voltage Symbol VDD VCC VDD-VEE1 VDD-VEE2 Supply voltage Input voltage Input current Output current Operating temperature range Storage temperature range VEE1, VEE2 VI II IO TA Tstg. -22 to +0.5 VEE2 - 0.5 to VDD2 + 0.5 10 10 -20 to +85 -55 to +125 V V mA mA C C Conditions Rated value -0.5 to +28 -0.5 to +7 -0.5 to +42 Unit V V V
RECOMMENDED OPERATING RANGES (TA = -20 C to +70 C, VSS = 0 V)
Parameter Supply voltage Supply voltage Supply voltage Supply voltage Symbol VDD VEE1 VEE2 VDD-VEE1 VDD-VEE2 Supply voltage Supply voltage VCC VCC For the 3.3 V logic input For the 5.0 V logic input 3.0 4.5 3.3 5.0 3.6 5.5 V V Conditions Min. 16 VEE2 -20 20 Typ. Max. 25 VEE2 + 10 0 40 Unit V V V V
Remark When shifting the level of VEE1 (driver supply voltage), satisfy the condition: VEE2 VEE1 VEE2 + 10 V Note that shifting the VEE1 level results in the ON-state output resistance and output fall time ratings being changed.
ELECTRICAL CHARACTERISTICS (TA = -20 C to +70 C, VDD = 20 V, VEE1 = VEE2 = -20 V, VCC = 3.3 0.3 V or 5.0 0.5 V, VSS = 0 V)
Parameter Input high voltage Input low voltage Output high voltage Output low voltage Output high current Output low current ON-state output resistance Input leakage current Dynamic drain current Symbol VIH VIL VOH VOL IXOH IXOL RON1 IIL IDD IEE ICC Conditions Other than VCHA Other than VCHA STVR(STVL), IOH = -40 A STVR(STVL), IOL = 40 A Xn, VX = VDD - 1 V Xn, VX = VEE1 + 1 V VX = VEE1 + 1 V or VDD - 1 V V1 = 0 V, 5.0 V, or 3.3 V VDD, fX = 31.5 kHz VEE1/2, fX = 31.5 kHz VCC, fX = 31.5 kHz 0.5 -0.5 50 1.5 660 1.0 1.0 -1.0 100 Min. 0.7VCC VEE2 VCC - 0.4 VSS Typ. Max. VCC 0.3VCC VCC VSS + 0.4 -1.5 Unit V V V V mA mA
A
mA mA
A
8
PD16650
SWITCHING CHARACTERISTICS (TA = -20 C to +70 C, VDD = 20 V, VEE1 = VEE2 = -20 V, VSS = 0 V, VCC = 3.3 0.3 V or 5.0 0.5 V)
Parameter STVR and STVL output delay Symbol tPHL1 tPLH1 Driver output delay tPHL2 tPLH2 td1 td2 Output rise time Output fall time Input capacitance Maximum clock frequency tTHL tTLH CI f X Conditions CL = 20 pF CLK STVR(STVL) CL = 220 pF CLK Xn CL = 220 pF, OE: L H CL = 220 pF, OE: H L CL = 220 pF CL = 220 pF TA = 25 C For cascade connection 100 Min. Typ. Max. 600 600 700 700 700 700 300 300 15 Unit ns ns ns ns ns ns ns ns pF kHz
TIMING REQUIREMENTS (TA = -20 C to +70 C, VDD = 20 V, VEE1 = VEE2 = -20 V, VSS = 0 V, VCC = 3.3 0.3 V or 5.0 0.5 V)
Parameter Clock pulse high width Clock pulse low width Data setup time Data hold time Symbol PWX(H) PWX(L) tsetup thold Conditions Duty = 50 % Duty = 50 % STVR(STVL) CLK CLK STVR(STVL) Min. 500 500 100 100 Typ. Max. Unit ns ns ns ns
Remark The logic input rise time (tr) and fall time (tf) must be within 20 ns (between 10 % and 90 % of the peak amplitude of the input).
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PD16650
SWITCHING CHARACTERISTIC WAVEFORM (R/L = HIGH)
1/f X PW X PW X VCC 50 % 50 % 50 % 50 % VSS
x
tsetup
thold VCC
VSS
tPLH2
tPHL2
90 % Xn 50 % 10 % tTLH tPLH1
90 % 50 % 10 % tTHL tPHL1 VOH 50 % 50 % VOL
STVL (STVR)
VCC OE 50 % 50 % VSS td1 td2
Xn
50 %
Xn
50 %
10
PD16650
RECOMMENDED MOUNTING CONDITIONS
When mounting this product, please make sure that the following recommended conditions are satisfied. For packaging methods and conditions other than those recommended below, please contact NEC sales personnel.
PD16650N-xxx
Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350 C; heating for 2 to 3 seconds; pressure 100 g (per solder) Temporary bonding 70 to 100 C; pressure 3 to 8 kg/cm 2; time 3 to 5 secs. Real bonding 165 to 180 C; pressure 25 to 45 kg/cm 2; time 30 to 40 secs. (when using the anisotropic conductive film SUMIZAC1003 of Sumitomo Bakelite, Ltd.)
ACF (Sheet-shape bonding agent)
Caution
To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more packaging methods at a time.
Reference NEC Semiconductor Device Reliability/Quality Control System (IEI-1212) Quality Grades to NEC's Semiconductor Devices (IEI-1209)
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PD16650
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product.
M4 94.11

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